BCD가산기의 verilog HDL설계
BCD가산기를 VHDL로 설계하여 출력이 정상대로 나옴을 확인하시오.</p>
<<입력값>>
A: 0 ~ 9
B: 0 ~ 9
캐리 C: 0, 1</span>
2010, Nov 07
`timescale 1ps / 1ps
module test;
reg c_in;
reg [3:0] y;
reg [3:0] x;
wire c_out2;
wire [3:0]sum;
wire [3:0]sum2;
wire [3:0] b2;
wire c;
wire c_out;
assign b2[0]=0;
assign b2[3]=0;
FourBitAdder A1(sum, c_out, x, y, c_in);
and(a,sum[3],sum[2]);
and(b,sum[3],sum[1]);
or(c,c_out,a,b);
assign b2[1]=c;
assign b2[2]=c;
FourBitAdder A2(sum2,c_out2,b2,sum,0);
//module FourBitAdder(sum, c_out, x, y, c_in);
initial
begin //SIGNAL x
x = 4'b0000;
#2500
x = 4'b0001;
#2500
x = 4'b0010;
#2500
x = 4'b0011;
#2500
x = 4'b0100;
#2500
x = 4'b0101;
#2500
x = 4'b0110;
#2500
x = 4'b0111;
#2500
x = 4'b1000;
#2500
x = 4'b1001;
#2500
x = 4'b0000;
#2500
x = 4'b0001;
#2500
x = 4'b0010;
#2500
x = 4'b0011;
#2500
x = 4'b0100;
#2500
x = 4'b0101;
#2500
x = 4'b0110;
#2500
x = 4'b0111;
#2500
x = 4'b1000;
#2500
x = 4'b1001;
#2500
;
end
initial
begin //SIGNAL y
y = 4'b0000;
#2500
y = 4'b0001;
#2500
y = 4'b0010;
#2500
y = 4'b0011;
#2500
y = 4'b0100;
#2500
y = 4'b0101;
#2500
y = 4'b0110;
#2500
y = 4'b0111;
#2500
y = 4'b1000;
#2500
y = 4'b1001;
#2500
y = 4'b0000;
#2500
y = 4'b0001;
#2500
y = 4'b0010;
#2500
y = 4'b0011;
#2500
y = 4'b0100;
#2500
y = 4'b0101;
#2500
y = 4'b0110;
#2500
y = 4'b0111;
#2500
y = 4'b1000;
#2500
y = 4'b1001;
#2500
;
end
initial
begin //SIGNAL c_in
c_in = 1'b0;
#25000
c_in = 1'b1;
#25000
;
end
initial
#50000
$finish;
endmodule
//** half Adder ************************
module halfadder(sum, c_out, x, y);
output sum, c_out;
input x, y;
wire a, b, c;
xor (sum, x, y);
and (c_out, x, y);
endmodule
//** Full Adder ************************
module fulladder(sum, c_out, x, y, c_in);
output sum, c_out;
input x, y, c_in;
wire a, b, c;
halfadder ha1(a, b, x, y);
halfadder ha2(sum, c, a, c_in);
or (c_out,c,b);
endmodule
//** 4-Bit Adder *****************************
module FourBitAdder(sum, c_out, x, y, c_in);
output [3:0] sum;
output c_out;
input [3:0] x, y;
input c_in;
wire c1, c2, c3;
fulladder fa0(sum[0], c1, x[0], y[0], c_in);
fulladder fa1(sum[1], c2, x[1], y[1], c1);
fulladder fa2(sum[2], c3, x[2], y[2], c2);
fulladder fa3(sum[3], c_out, x[3], y[3], c3);
endmodule