반가산기 전가산기 병렬가산기의 Verilog HDL설계
2010, Nov 07
반가산기 및 전가산기를 부품으로 하여 병렬가산기를 설계하시오
//** half Adder ************************
module halfadder(sum, c_out, x, y);
output sum, c_out;
input x, y;
wire a, b, c;
xor (sum, x, y);
and (c_out, x, y);
endmodule
//** Full Adder ************************
module fulladder(sum, c_out, x, y, c_in);
output sum, c_out;
input x, y, c_in;
wire a, b, c;
halfadder ha1(a, b, x, y);
halfadder ha2(sum, c, a, c_in);
or (c_out,c,b);
endmodule
//** 4-Bit Adder *****************************
module FourBitAdder(sum, c_out, x, y, c_in);
output [3:0] sum;
output c_out;
input [3:0] x, y;
input c_in;
wire c1, c2, c3;
fulladder fa0(sum[0], c1, x[0], y[0], c_in);
fulladder fa1(sum[1], c2, x[1], y[1], c1);
fulladder fa2(sum[2], c3, x[2], y[2], c2);
fulladder fa3(sum[3], c_out, x[3], y[3], c3);
endmodule